N-gate transistor

ABSTRACT

A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.

FIELD

The present invention relates generally to the field of semiconductortechnology and, more specifically, to formation of a transistor.

BACKGROUND

In the semiconductor fabrication industry, it is a common goal to makean integrated circuit progressively smaller, faster, and more efficient.However as the basic circuit devices, such as transistors, get smaller,the reduced device dimensions cause otherwise tolerable electricaleffects to become unacceptably large. One such undesirable effect is thedifficulty of the gate of the transistor to precisely control currentflow through the body terminal (i.e, the channel region) of thetransistor. More specifically, as shown in FIG. 1A, as a transistor'sdimensions grow smaller source/drain regions 10 become very close. Thechannel distance (d) is very small and consequently excessive currenttends to leak from source/drain regions 10 outside the control of thegate electrode 12. Additionally, the ever increasing encroachment of thesource/drain regions 10 underneath the gate electrode 12 tends to causeadditional capacitance leading to other undesirable short channeleffects.

Some devices have been formed in an attempt to correct undesirable shortchannel effects. One such device is the tri-gate device. A tri-gatedevice, as shown at FIG. 1B, includes source/drain regions 20, on aninsulator layer 22 overlying a substrate 24. A gate electrode 26 isformed to surround a portion of the source/drain regions 20 defining aninternal channel region 50 within the device connecting. A cross-sectionof this channel region 50 is shown at FIG. 1C, along the gate width ofthe device. As shown in FIG. 1C, the channel region 50 has three planarwalls (61, 62, and 63) that are connected to the gate electrode 26 via agate dielectric 65. Two of the walls 61 and 62 are vertical while onewall 63 is horizontal. Each of the three planar walls 61, 62 and 63 istermed a “gate”, G₁, G₂, and G₃ respectively, since the gate electrode26 makes electrical connection to each, and, thus, can provide a voltageto each side. It was believed that the three gates allowed a fulldepletion of the device. The tri-gate device is advantageous for severalreasons. For example, because of its three-gate design, the gateelectrode 26 can control the channel region with more precision.Additionally, because of its nature as a semiconductor-on-insulatordevice, capacitances are lower at source/drain regions 20, thusimproving the device switching speed.

However, despite these advantages, technology continues to progress andtransistor designs continue to shrink. Consequently, even the tri-gatedesign begins to face challenges in controlling current in the channelregion, and other short channel effects.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention are illustrated by way of exampleand should not be limited by the figures of the accompanying drawings inwhich like references indicate similar elements and in which:

FIG. 1A-1C illustrate transistors according to the prior art;

FIG. 2 is a cross-sectional illustration of a body terminal of atransistor device according to one embodiment of the invention;

FIG. 3A is a three-dimensional dissected view of asemiconductor-on-insulator (SOI) transistor 300 according to oneembodiment of the invention;

FIG. 3B is a cross sectional view of the transistor 300 along the gatewidth;

FIG. 3C is a charge density illustration of a cross sectional view ofthe transistor 300 along the gate width;

FIG. 3D is a current-to-voltage graph for the transistor 300;

FIG. 4A-4J illustrate a method of forming the transistor 300 accordingto one embodiment of the invention;

FIG. 5 is an illustration of a transistor 500 having a three-tieredstair-step structure according to another embodiment of the invention;

FIG. 6A-6D illustrate a method of forming the transistor 500 accordingto one embodiment of the invention;

FIG. 7A-7B illustrate is a MOS, or insulated gate, field-effecttransistor 700 according to one embodiment of the invention; and

FIG. 8A-8G illustrate a method of forming the transistor 700, accordingto one embodiment of the invention.

DETAILED DESCRIPTION

Described herein is an “n” gate transistor. In the following descriptionnumerous specific details are set forth. One of ordinary skill in theart, however, will appreciate that these specific details are notnecessary to practice embodiments of the invention. While certainexemplary embodiments of the invention are described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative and not restrictive of the current invention, andthat this invention is not restricted to the specific constructions andarrangements shown and described since modifications may occur to thoseordinarily skilled in the art. In other instances well knownsemiconductor fabrication processes, techniques, materials, equipment,etc., have not been set forth in particular detail in order to notunnecessarily obscure embodiments of the present invention.

Embodiments of the invention described herein include a transistordevice including a body terminal (i.e., “channel region”) with many(more than two) corners, or protruding angled edges. The protrudingangled edges extend through the entire length of the channel region,connecting source/drain regions. The protruding angled edges allow abuild up of inversion charge within an angled corner and thus act aselectrically conducting conduits inside the channel region.Consequently, according to embodiments of the invention describedherein, the many angled edges may be referred to herein as electricallyconducting channel conduits, or “channel conduits” for short, becauseeach angled edge is to act like a conduit for inversion charge, toenhance the flow of electricity through the channel region.

FIG. 2 is a cross-sectional illustration of a body terminal (“channelregion”) of a transistor device according to one embodiment of theinvention. Referring to FIG. 2, the channel region has many protrudingcorners 225, or angled edges. Additionally, the channel region is formedfrom a semiconductor material 202 to have a stair-step shaped structure230. The stair-step structure 230 is a stair-step shaped polyhedron thatincludes at least two stair-step levels, “upper” stair-step level 240and “lower” stair-step level 250. The upper stair-step level 240includes at least one stair step 213. As shown in FIG. 2, the stair step213 may have two vertical sidewalls 216 and one horizontal topwall 217.The lower stair-step level 250 also includes at least one stair step 214subjacent to the upper stair step 213. As shown in FIG. 2, the lowerstair-step level may include two lower stair steps 214 straddling theupper stair step 213. Thus, the stair-step structure 230 may includeseven planar walls (216, 217, 226, and 227). The seven planar walls(216, 217, 226, and 227) may connect at approximately right angles tothe form four corners 225, which are cross-sectional representations ofangled edges, or channel conduits, that extend through a portion of thesemiconductor material 202 in a direction that extends outside of thecross-sectional plane shown in FIG. 2. The seven planar walls (216, 217,226, and 227) are each long enough to maximize a build-up of inversioncharge inside the abruptly angled inner contour of the corners 225 andshort enough to minimize the amount of semiconductor material 202 neededto create the stair-step structure 230, hence minimizing the overallsize of the stair-step structure.

FIG. 3A is a three-dimensional dissected view of asemiconductor-on-insulator (SOI) transistor 300 according to oneembodiment of the invention. Referring to FIG. 3A, the transistor 300includes source/drain regions 310, a gate electrode 350, a gatedielectric 340, and a channel region 355 enclosed within the gatedielectric 340 and surrounded by the gate electrode 350. Thesource/drain regions 310, and the channel region 355 connecting thesource/drain regions 310, are formed of the same basic semiconductormaterial, such as silicon or germanium, and hence the source/drainregions 310 and the channel region 355 may be collectively referred to,herein, as a semiconductor “body” 330. According to FIG. 3A, thesemiconductor body 330 is formed upon an insulator layer 304 and maymore aptly be referred to as a “floating” semiconductor body, or perhapseven a semiconductor “island” because it is entirely isolated from anunderlying substrate 302 by the insulator layer 304. The substrate 302may be a semiconductor material, such as monocrystalline silicon.

FIG. 3B is a cross sectional view of the transistor 300 along the gatewidth according to one embodiment of the invention. Referring to FIG.3B, according to one embodiment of the invention, the semiconductor body330 is formed to have many (more than two) protruding angled edges 325and many planar walls 327. According to the embodiment of the inventionshown in FIG. 3B, the semiconductor body 330 has at least fourprotruding angled edges 325 that jut, poke, project, or in some wayabruptly protrude into the gate electrode 350. Additionally, accordingto the embodiment of the invention shown in FIG. 3B, the semiconductorbody 330 has seven or more planar walls 327 that border the gateelectrode 350 within the channel region 355. The planar walls 327 thatare surrounded by the gate electrode 350 may be referred to, generally,as “channels” since they are effectively controlled by the gateelectrode 350, separated only by the gate dielectric 340. Consequently,the embodiment of the invention shown in FIG. 3A-3B may be more aptlyreferred to as a seven-gate device, or a “sept-gate” device, since thegate electrode 350 and the planar walls 327 of the channel region 355combine to form seven electrical gate connections.

FIG. 3C is a charge density illustration of a cross sectional view ofthe transistor 300 along the gate width according to one embodiment ofthe invention. The charge density graph shows different areas of chargedensity when a voltage has been applied to the gate electrode 350. Acenter area 360 shows a portion of relatively little electricalactivity, or a “non-depleted” area. Closer to the walls 327 is anotherarea 361 of relatively moderate electrical activity. However, within theprotruding angled edges 325 are areas 363 of high electrical activity.Areas 363 comprise inversion charge confined primarily to the abruptlyangled curvature of the protruding angled edges 325, and taper offtoward the inverted corners 329 and the bottom corners 339. Theseprotruding angled edges 325, may be referred to as “channel conduits325”, wherein electrical charge builds up and flows between source/drainregions of the device. With four channel conduits 325, the gateelectrode 350 has a very strong control over the electrical chargethrough source/drain regions 310 that are illustrated in FIG. 3A. Sincethe strongest charge density is constrained to the protruding anglededges that are under strong gate field control, there is little effectfrom the drain field on this charge, resulting in reduced short-channeleffects.

Still referring to FIG. 3C, each wall 327 of the transistor should beformed to have a length that maximizes the effect of the inversioncharge within the channel conduits 325. At the same time, the walllengths should be short enough to minimize the amount of semiconductingmaterial used to form the device. As shown in FIG. 3C, the length (Y) ofthe horizontal walls and the length (Z) of the vertical walls aredesigned so that the inversion charge reduces to an insignificant amountat the inverted corners 329 and bottom corners 339. The lengths (Y andZ) may vary according to the design requirements of the device and theoperational voltage applied to the gate electrode. In one embodiment ofthe invention, however, the lengths of the horizontal walls may beapproximately equal to the depletion depth. However, these dimensionsmay be independently optimized for best overall performance of thedevice.

FIG. 3D is a current-to-voltage graph for the transistor 300 accordingto one embodiment of the invention, according to simulation. As shown inFIG. 3D, the current 390 through the channel region for the seven-gatetransistor 300, as described above, is significantly better than thecurrent 380 of a conventional tri-gate device, for the same gateelectrode voltage. Through a range of normal operations voltages, thecurrent 390 for the seven gate transistor 300 is expected to out performthe current 380 of the conventional tri-gate device by 20%.

FIG. 4A-4J illustrate a method of forming the transistor 300 accordingto one embodiment of the invention. The method begins, in FIG. 4A, withforming an insulator layer 304 over a substrate 302 and forming asemiconductor layer 406 over the insulator layer 304. The compositestack of substrate 302, insulator layer 304, and semiconductor layer 406may be formed by known processes such as thermal bonding techniques,cutting techniques, separation by implantation of oxygen (SIMOX)techniques, or any combination thereof. The insulator layer 304 mayinclude any dielectric material, such as silicon oxide or other high kdielectrics. The substrate 302 may be a conductor or semiconductor suchas silicon (Si), silicon germanium (SiGe), silicon germanium carbide(SiGeC), silicon carbide (SiC), polysilicon, epitaxial silicon,amorphous silicon, or any combination thereof. The semiconductor layer406 may comprise any semiconductor material used to form a transistordevice. Examples of semiconductor materials may include the samematerials as those already mentioned for the substrate 302 and furtherincluding antimony, arsenic, boron, carbon, germanium, selenium,silicon, sulfur, and tellurium. Other semiconductor materials mayinclude gallium arsenide, and indium antimonide. In one embodiment ofthe invention, the semiconductor layer 406 comprises lightly dopedmonocrystalline silicon while the substrate 302 comprises heavily dopedmonocrystalline silicon doped to a different conductivity than thesemiconductor layer 406. The thickness (h) of the semiconductor layer406 depends on the desired height of a subsequently formed channelregion as well as the desired height of the vertical sidewalls of thestair-step structure that will form the sept-gate channel region. Thelayer thickness (h) is technology dependent, and may be optimized tomeet some constraint, or may be limited by process capabilities. Forexample, the insulator 304 thickness is about 150 nm and thesemiconductor layer 406 has a thickness of about 40 nm when the gatelength is 60 nm. The thicknesses of the insulator 304 and thesemiconductor layer 406 can be decreased as the gate length decreases.

As shown in FIG. 4B, a protective mask layer 408 is formed from amaterial different in material composition than the semiconductor layer406 and the insulator layer 304. Specifically, the material of theprotective mask layer 408 may be a material composition that can beetched by chemistry that will etch the protective mask layer 408 butthat will not etch the underlying semiconductor layer 406 or theinsulator layer 304. In the embodiment of the invention shown in FIG.4B, the protective mask layer 408 is formed from a material typicallyused as a hardmask, such as an oxide, nitride, oxynitride, or anycombination thereof. In one embodiment of the invention, the protectivemask layer 408 is a nitride material. Consequently, according toembodiments of the invention, the protective mask layer 408 may also bereferred to as a hardmask layer 408. The hardmask layer 408 may beformed by any known method of forming a thin film including chemicalvapor deposition (CVD), plasma-assisted CVD, evaporation, sputtering,atomic layer deposition, chemical solution deposition, or thermalgrowing processes such as oxidation, nitridation or oxynitridation.

Next, as shown in FIG. 4C, a photoresist mask 410 may be formed on thehardmask layer 408 via known photolithography techniques includingdepositing a photoresist material, masking the photoresist material,exposing the photoresist material, and developing the exposedphotoresist material to form the patterned photoresist mask 410. Thephotoresist mask 410 should be formed to a desired width (w1) that willrepresent the width of an upper stair step, as described in conjunctionwith FIG. 4E below.

Next, as shown in FIG. 4D, the pattern of the photoresist mask 410 isthen transferred to the hardmask layer 408 via an etching techniqueutilizing an etchant 412 with a particular chemistry that etches thehardmask layer 408 but that does not etch the semiconductor layer 406.The photoresist mask 410 protects the underlying portion of the hardmasklayer 408 from the etchant 412, thus forming a “hardmask” 408. Hardmask408 has the same width (w1) as the photoresist mask 410.

Referring now to FIG. 4E, after photoresist layer 410 is removed, afirst portion of the semiconductor layer 406 is etched by etchant 414 toa first thickness, in alignment with the hardmask 408, by a first timedetch, to form a first stair-step level 440. Etching techniques mayinclude reactive ion etching (RIE), plasma etching, ion beam etching, orother known etching techniques. The etchant 414 may includes a chemistrythat etches the semiconductor layer 406 but that does not etch thehardmask 408. The semiconductor layer 406 is not etched entirely, but istimed so that only half of the thickness (h/2) of the semiconductorlayer 406 is etched. For a semiconductor layer 406 having a thickness h,etchant 414 may have a given etch rate of X nm/min. Thus, the time forthe etch would be equal to (h/2)/(Xnm/min) so that the semiconductorlayer 406 is not overetched beyond h/2. In one embodiment of theinvention, the semiconductive layer 406 comprises silicon; hence, anexemplary etchant 414 may include an etch chemistry layer such as HBr,SF₆, Cl₂, CF₄, and mixtures of these gases with H₂, Ar, He, and 0₂ toetch silicon.

During etching, the hardmask 408 protects the portion of the underlyingsemiconductor layer 406 directly underneath the hardmask 408 from theetchant 414, thus forming a first, or “upper”, stair step level 440. Theupper stair-step level 440 has a plateau shaped stair step 413 thatincludes two vertical sidewalls 416 and one horizontal topwall 417. Thelength of the vertical sidewalls 416 is equivalent to h/2. The width(w₁) of the upper horizontal topwall 417 is the same width as that ofthe hardmask 408. Hence, as described previously, when the hardmask 408is formed, the width of the hardmask 408 should be formed to the desiredwidth (w1) of the upper stair step 413.

Next, as shown in FIG. 4F, spacers 420 are formed adjacent to, and alongthe entire sidewall length, of the vertical sidewalls 416 and along thevertical sidewalls 418 of the hardmask 408. The spacers 420 may comprisea material that is different from the material of the semiconductorlayer 406, the underlying insulator layer 304, and the hardmask 408. Inone embodiment of the invention, the material of the spacers 420 may bea nitride, an oxide, or a combination of a nitride and an oxide, such asa nitride/oxide, or an oxide/nitride/oxide (ONO) composite formed by arapid thermal oxidation process. Spacers 420 may be formed according toknown techniques of depositing a spacer material over the hardmask 408and over the surface 421 of the unetched portion of the semiconductorlayer 406. Know methods include CVD, PVD, and other thin film depositionmethods. Once deposited, the spacer material may be vertically etched,such as via an anisotropic etching technique, so that the spacermaterial is etched primarily in a vertical fashion, but notsubstantially etched in a horizontal fashion, thus leaving spacers 420along the vertical sidewalls 416 and 418. The formation of the spacers420 should include forming the spacers to have a bottom width, w2, hencethe thickness of the spacer material should be deposited to a thicknessof approximately width w2. The width, w2, is of the lower-most portionof the spacers 420 that touches the surface 421 of the unetched portionof the semiconductor layer 406. The width, w2, should correspond to thewidth of lower stair steps that will be subsequently formed subjacent tothe upper stair step 413. In one embodiment of the invention, the width,w2, is approximately equal to the width, w1, of the upper stair step413.

Next, as illustrated in FIG. 4G, the method continues with etching asecond portion of the semiconductor layer 406 in alignment with thespacers 420, to a second thickness, to form a second stair-step level450. The hardmask 408 continues to protect the upper stair step 413 frombeing etched. As illustrated in FIG. 4G, the remainder of thesemiconductor layer 406 is etched with an etchant 422 having a chemistrythat etches the semiconductor layer 406 but that does not significantlyetch the spacers 420, the hardmask 408 or the underlying insulator layer304. The etch stops upon the upper surface 423 of the insulator layer304.

The result is the formation of the second, “lower” stair-step level 450.The lower stair-step level 450 includes two stair steps 414 formedsubjacent (adjacent to and below) the plateau-shaped upper stair step413. The two adjacent stair steps 414 connect to the upper stair step413 at inverted corners 429. In other words, lower horizontal topwalls427 of the lower stair steps 414 connect to the vertical sidewalls 416of the upper stair step 413 at inverted corners 429. The width of thelower horizontal topwalls 427 is the same as the width (w2) of thespacers. The height of the lower vertical sidewalls 426 is equivalent toh/2, or approximately half the original height of the semiconductorlayer 406. As shown in FIG. 4G, semiconductor layer 406 is now referredto as semiconductor body 330 having a stair-step shaped structure.

Next, as illustrated in FIG. 4H, the spacers 420 and the hardmask 408are removed according to known techniques. The chemistries necessary toremove the hardmask 408 and the spacers 420 do not remove thesemiconductor body 330 since the semiconductor body 330 comprises amaterial that is different from both the hardmask 408 and the spacers420. Still referring to FIG. 4H, the semiconductor body 330 includes twosets of protruding corners 424, 425. Two upper protruding corners 425are formed where the upper horizontal topwall 417 meets with uppervertical sidewalls 416. Two lower protruding corners 424 are formedwhere the two lower horizontal topwalls 427 meet with the two lowervertical sidewalls 426. The four corners 424, 425 represent anglededges, or channel conduits, at approximate right angles (90°), thatextend between source/drain regions through the semiconductor body 330.

Next, a gate dielectric 340 as illustrated in FIG. 4I and a gateelectrode 350 as illustrated in FIG. 4J are formed to border thevertical and horizontal topwalls (426, 427, 416, and 417). Referringfirst to FIG. 4I, a gate dielectric 340 is formed. In one embodiment ofthe invention, the gate dielectric 340 may be formed from any insulativematerial used for insulating the semiconductor body 330 from the gateelectrode 350. In one embodiment of the invention, the gate dielectric340 may be silicon oxide (e.g., SiO₂). In other embodiments of theinvention, however, the gate dielectric 340 may comprise a material witha dielectric constant (k) substantially higher than the dielectricconstant of silicon dioxide (i.e., higher than k=3.9). Exemplary high-kmaterials used in the formation of integrated devices include metaloxides (Al₂O₃, ZrO₂, HfO₂, TiO₂, Y₂O₃, La₂O₃, etc.), ferroelectrics(PZT, BST, etc.), amorphous metal silicates (Hf, Zr), amorphous silicateoxides (HfO₂, ZrO₂), and paralectrics (Ba_(x)Sr_(1-x)TiO₃,PbZr_(x)Ti_(1-x)O₃). The gate dielectric 340 may be formed by a thermalgrowing process such as oxidation, nitridation or oxynitridation.

Referring next to FIG. 4J, the gate electrode 350 is formed in contactwith the gate dielectric 340 and the insulator layer 304. The gateelectrode 350 may comprise any conductive material, such as any one of,or a combination of, metal, metal compound, polysilicon, amorphoussilicon, or other known conductors or semiconductor materials. In theembodiment of the invention shown in FIG. 4J, the gate electrode 350comprises polycrystalline silicon (“polysilicon”) heavily doped toimprove conductivity. The gate electrode 350 may be formed by chemicalvapor deposition (CVD), physical vapor deposition (PVD), or other knownmethods of depositing a thin film. A chemical mechanical polish (CMP)may follow to planarize the top of the gate electrode 350.

The multiple sets of angled edges (424, 425) protrude into the gateelectrode 350 and extend through the entire length of the channel regionwithin the semiconductor body 330. The abrupt, approximately 90° angle,of the angled edges, 424, 425, allows for a build up of inversion chargewithin the area close to the angled edges 424 and 425. Each angled edgeacts like a conduit for inversion charge, enhancing the flow ofelectricity through the channel region within the semiconductor body330. Thus, the many angled edges, 424, 425, may also be referred toherein as “channel conduits”, because the function of each angled edgeis to act like a conduit for charge within the channel region of thesemiconductor body 330.

Still referring to FIG. 4J, several gates (G1-G7) are thus formed. Theterm “gate” is utilized herein to mean a portion of the gate electrode350 that is sufficiently close to the semiconductor body 330 to inducean electrically conductive channel. Shown in FIG. 4J, there are 7 suchgates, thus allowing seven different surface areas where current canflow from source to drain. As a result, charge is induced between thesource/drain regions in 7 channels along the semiconductor body 330 bythe voltage applied at gates G1-G7, thus increasing the effectiveelectrical conductivity of the semiconductor body 330, inducing anenhanced flow of electrons through the semiconductor body 330. The flowof electrons, however, becomes highly increased at the angled edges,424, 425, that protrude into the gate electrode 350. As a result,electrons are permitted to flow through the channel region of thesemiconductor body 330 in a very controlled manner and at a higher ratethan in a transistor device that does not have the many angled edges.Consequently, the gate length of the transistor 300 can be very smalldown to around 10 nm, yet the gate electrode 350 has excellent controlof the current therein.

FIG. 5 is an illustration of a transistor 500 having a semiconductorbody 530 with a three-tiered stair-step structure, according to anotherembodiment of the invention. Transistor 500 also has an insulator 304, asubstrate 302, a gate dielectric 340, and a gate electrode 350. FIG.6A-6D illustrate a method of forming the transistor 500 according to oneembodiment of the invention. Similar techniques described in conjunctionwith FIG. 4A-4J may be utilized to form transistor 500, as shown in FIG.6A-6D. Referring to FIG. 6A, a hardmask 408 is formed upon the stack ofsemiconductor layer 406, insulator 304, and substrate 302. FIG. 6B-6Dshow the semiconductor layer 406 being etched with three timed etches(similar to the two timed etches shown in FIG. 4A-4J). FIG. 6B-6D alsoshows forming two sets of spacers 420 (similar to the formation of theone set of spacers 420 in FIG. 4A-4J.) The three timed etches showniteratively in FIG. 6B-6D, are timed so that the etchant 614 of eachiterative etching procedure only etches the semiconductor layer 406 to athickness of h/3. The resultant semiconductor body 530 has 11 planarwalls and, therefore, may form a transistor having 11 gates.

In comparing the two methods described in FIG. 4A-4J and FIG. 6A-6D, itcan be seen that a semiconductor body can be formed to include anynumber (“n”) of gates according to various embodiments of the invention.Hence, more generally, an n-gate structure is described herein. Theletter “n” represents a variable number of gates. As described above, inone embodiment of the invention, the transistor can be formed to haveseven or more gates. For any number of gates, n, a particular number ofstair-step levels (“s”) is required. More specifically, for any “n”gates, s=((n+1)/4) stair-step levels are required to be formed.Consequently, during formation, semiconductor layer 406 should beetched, during each iterative timed etch, a vertical distance of h/s,where “h” represents the thickness of the semiconductor layer 406 asoriginally formed before any timed etches occur, and “s” represents thenumber of stair-step levels to be formed. The result will be asemiconductor body having a channel region with a particular number ofprotruding angled edges (“e”), or channel conduits quantified bye=((n+1)/2), or e=2s.

Additionally, embodiments of the invention are not limited tosemiconductor-on-insulator (SOI) technology as demonstrated above. Manyprotruding angled edges can be formed into the channel region of atypical, non-SOI field-effect-transistor (FET), such as a junction FET(JFET) or a metal-oxide-semiconductor FET (MOSFET) (also known as aninsulated-gate FET). FIG. 7A-7B illustrates a MOS, or insulated gate,field-effect transistor 700 according to one embodiment of theinvention. FIG. 7A is a three-dimensional dissected view of a MOS, orinsulated gate, FET 700 showing cross-sectional dissections of thedevice along both the gate width and the gate length of the transistor700. FIG. 7B is a cross section of the transistor 700 along the gatelength, hence representing a mirror image representation of transistor700 as shown in FIG. 7A, absent the gate width dissection.

Referring to FIG. 7A-7B, the transistor 700 includes a substrate 702, agate dielectric 704, a gate electrode 706, and source/drain regions 708.Isolation regions 710 may be formed adjacent to the source/drain regions708 to isolate the transistor 700 from other electronic devices that maybe integrated into the substrate 702. Spacers 712 may also be formedadjacent to the gate electrode 706 according to known processes.

Underlying the gate electrode 706 is a channel region 705. The channelregion 705 includes the portion of the substrate 702 directly beneaththe gate electrode 706 that connects the source/drain regions 708. Thechannel region 705 of the transistor 700 includes a stair-step structure703 formed therein. In the embodiment of the invention illustrated inFIG. 7A, a plurality of stair-step structures 703 have been formed intothe channel region 705. The stair-step structures 703 include multiple(more than one) stair-step levels, including an upper stair-step level740 and a lower stair-step level 750. The stair-step structures 703further include many angled edges 725 protruding into the gate electrode706. The many angled edges 725 are to act as electrically conductingconduits wherein inversion charge can build up inside the angled innercontour of the edge when a charge is applied to the gate electrode 706and through which electrical current can flow between source/drainregions 708.

FIG. 8A-8G illustrate a method of forming the transistor 700, accordingto one embodiment of the invention, along the gate width cross-section.Referring first to FIG. 8A, a protective mask layer (“hardmask layer804”) is formed on a semiconductor substrate 702. The hardmask layer 804includes a material that is different from the material of the substrate702 so that the hardmask layer 804 may be etched with a chemistry thatis selective to the substrate 702. Upon the hardmask layer 804, aphotoresist pattern 808 is formed. The photoresist pattern 808 may beformed according to known techniques. The width (w3) of the photoresistpattern 808 will determine the width of a subsequently formedstair-step, as described in conjunction with FIG. 8C below. The distance(d1) between neighboring photoresist patterns 808 should take intoaccount the width of a total number of stair-step levels to besubsequently formed into the substrate 702. In other words, for a givennumber of stair step levels (“s”) to be formed, the distance, d1, shouldbe at least greater than s times the width w3, or d1>s ×(w3). Forexample, if two stair-step levels will be formed into the substrate 702,then the distance, d1, should be great enough to allow for the formationof two stair steps on either side of the photoresist patterns 808, hencedistance, d1, would be greater than two times (2×) the width w3.

Referring next to FIG. 8B, the dimensions of the photoresist pattern 808are transferred to the hardmask layer 804 according to known etchingtechniques. According to one embodiment of the invention, thephotoresist pattern 808 is etched with a reactive ion etching techniquethat utilizes an etch chemistry that etches the hardmask layer 804 butdoes not etch the photoresist mask 808 nor the underlying substrate 702.The photoresist mask 808 may then be removed, resulting in hardmasks 804having the width w3.

Next, as shown in FIG. 8C, the substrate 702 is etched vertically withan etchant 810 that etches the substrate 702 but does not etch thehardmasks 804 to form a first, “upper” stair step 813. The upper stairstep 813 includes two vertical sidewalls 816 and a vertical topwall 817.The etch is carefully timed so that only a certain vertical distance(“h1”) is etched. Vertical distance, h1, defines the height of thevertical sidewalls 816. Consequently, upper stair step 813 has a plateaushape with the vertical sidewalls 816 being a given height, h1, and withthe horizontal topwall 817 being a given width, (w3).

Next, as shown in FIG. 8D, spacers 820 are formed along the entiresidewall length of the upper stair step 813 and along the entiresidewall length of the hardmask 804. The width (w4) of the spacers 820will define the width of subsequently formed lower stair steps describedin conjunction with FIG. 8E below. Consequently, spacers 820 may beformed by depositing a spacer material, different from the material ofthe hardmask 804 and the substrate 702, that can be etched with achemistry that will not etch the hardmask 804 nor the substrate 702. Thespacer material may be deposited to a thickness of approximately w4,then anisotropically etched so that the resultant spacer 820 has a widthof approximately w4. In one embodiment of the invention, the width, w4,is approximately equal to the width, w3, of the upper stair step 813.

Next, as shown in FIG. 8E, the substrate 702 is again etched verticallywith an etchant 821 that etches the substrate 702 but does not etch thehardmasks 804 or the spacers 820, to form a second level of “lower”stair steps 814. The lower stair steps 814 include vertical sidewalls826 and horizontal topwalls 827. The etch is carefully timed so thatonly a certain vertical distance (“h2”) is etched. Vertical distance,h2, defines the height of the vertical sidewalls 826. Consequently,lower stair steps 814 include sidewalls 826 with a given height, h2, andhorizontal topwalls 827 with a given width, w4.

When the spacers 820 and the hardmasks 804 are removed, as shown in FIG.8F, the result is multiple stair-step structures 703 having multiplestair-step levels 740, 750. A first, upper level 740, includes the upperstair step 813. A second, lower level 750, includes the lower stairsteps 814. Stair-step structures 703 still constitute the same materialmass as the substrate 702. Angled edges 725 are formed on each level 740and 750. The angled edges 725 of the upper level 740 are formed at theconnection of the upper vertical sidewalls 816 and the upper horizontaltopwall 817. The angled edges 725 of the lower level 750 are formed atthe connection of the lower vertical sidewalls 826 and the lowerhorizontal topwalls 827. Adjacent to each stair-step structure 703 arespaces 855 that separate the stair-step structure 703 by a givendistance, d2. The spaces 855 must be long enough in length, d2, toestablish a corner 826/827, but not so long as to be a significantfraction of the device width.

As shown in FIG. 8G, a gate dielectric 704 is formed over the stair-stepstructures 703 and on the spaces 855 to either sides of the stair-stepstructures 703. Following the formation of the gate dielectric 704, agate electrode 706 is formed over the gate dielectric 704. In oneembodiment of the invention, the gate dielectric 704 may be formed fromany insulative material used for insulating the gate electrode 706 fromthe substrate 702. In one embodiment of the invention, the gatedielectric 704 may be silicon oxide (e.g., SiO₂). In other embodimentsof the invention, however, the gate dielectric 704 may comprise amaterial with a high dielectric constant. Gate dielectric 704 may beformed by a thermal growth process.

After the formation of the gate electrode 706, the gate electrode 706may be subjected to a CMP process and impurity doping may occur to thesurface of the substrate 702 where source/drain regions exist as shownpreviously in FIG. 7B, where the junctions are formed by conventionalimplants, by outdiffusion, or by epitaxial growth.

Several embodiments of the invention have thus been described. However,those ordinarily skilled in the art will recognize that the invention isnot limited to the embodiments described, but can be practiced withmodification and alteration within the spirit and scope of the appendedclaims that follow.

1. An apparatus, comprising: a channel region connecting source/drainregions of a transistor, the channel region having many protrudingangled edges that extend between, and connect, the source/drain regions,the many protruding angled edges to act as electrically conductingchannel conduits between source/drain regions.
 2. The apparatus of claim1, further comprising: a gate electrode coupled to the channel region,the protruding angled edges protruding into the gate electrode and theprotruding angled edges having an angled inner contour wherein inversioncharge can build up when a voltage is applied to the gate electrode. 3.The apparatus of claim 1, wherein the channel region has a stair-stepshape along the device width.
 4. The apparatus of claim 3, wherein thestair-step shape includes seven or more planar walls that are longenough to allow inversion charge to effectively build up inside the manyprotruding angled edges.
 5. The apparatus of claim 4, wherein the sevenor more planar walls are approximately equal in length.
 6. The apparatusof claim 1, wherein the many protruding angled edges are substantiallyat right angles.
 7. An apparatus, comprising: an insulator layeroverlying a substrate; a semiconductor-on-insulator (SOI) semiconductorbody overlying the insulator layer, the semiconductor body havingsource/drain regions and a channel region connecting the source/drainregions, the channel region of the semiconductor body comprising sevenor more planar walls; and a gate electrode formed with a portionsurrounding the channel region, the gate electrode conforming to theshape of the channel region thus defining a gate electrode having sevenor more transistor gates.
 8. The apparatus of claim 7, wherein thesemiconductor body is a stair-step shaped polyhedron comprising an upperstair step and two lower side stair steps straddling the upperstair-step.
 9. The apparatus of claim 8, wherein the upper stair stepincludes two upper vertical sidewalls connected at right angles to oneupper horizontal topwall, and the two lower side stair steps eachinclude one lower vertical sidewall connected at a right angle to onelower horizontal top wall, each of the lower horizontal top wallsconnected at a right angle to one of the upper vertical sidewalls of theupper stair step.
 10. The apparatus of claim 7, wherein thesemiconductor body comprises four or more outwardly protruding edgesinside which inversion charge can build up when charge is applied to theseven or more transistor gates.
 11. The apparatus of claim 10, whereinthe seven or more planar walls of the channel region are each longenough to maximize inversion charge inside the electrically conductingchannel conduits and short enough to minimize the size of thesemiconductor body.
 12. The apparatus of claim 7, wherein the at leastseven planar walls of the channel region are approximately equal todepletion depth.
 13. An apparatus, comprising: source/drain regionsformed into a substrate, the source/drain regions connected by a channelregion; a gate dielectric overlying the channel region; and a gateelectrode overlying the gate dielectric, the channel region having astair-step shape with multiple stair steps along the device width, andthe gate electrode and the gate dielectric having a shape conforming tothe stair-step configuration of the channel.
 14. The apparatus of claim13, wherein the channel region includes four or more angled edgesprotruding into the gate electrode, the four or more angled edges to actas electrically conducting channel conduits.
 15. The apparatus of claim14, wherein the angled edges extend between, and connect, thesource/drain regions, and each angled edge includes an angled innercontour wherein inversion charge can build up when a voltage is appliedto the gate electrode.
 16. An integrated circuit, comprising: asemiconductor substrate; and a transistor structure overlying thesubstrate, the transistor structure including a source/drain regions, achannel region connecting the source/drain regions, and a gate electrodecoupled to the channel region, the channel region having many abruptlyangled edges protruding into the gate electrode, the many abruptlyangled edges to act as electrically conducting channel conduits.
 17. Theintegrated circuit of claim 16, wherein the many abruptly angled edgeshaving an abruptly angled inner contour wherein inversion charge canbuild up when a voltage is applied to the gate electrode.
 18. Theintegrated circuit of claim 16, wherein the channel region has astair-step shape.
 19. The integrated circuit of claim 18, wherein thestair-step shape includes seven or more planar walls that are longenough to allow inversion charge to effectively build up inside the manyabruptly angled edges.
 20. The integrated circuit of claim 18, whereinthe seven or more planar walls are approximately equal in length todepletion depth.
 21. The integrated circuit of claim 16, wherein themany abruptly angled edges are substantially at right angles. 22-27.(canceled)